According to the same document that we mentioned here, AMD seems to have integrated the L3 cache into the northbridge part of its K10 architechure. This might seem odd at first, but it does sort of make sense when you consider that the L3 cache is shared between each of the two or three CPU cores.

Since each core already has L1 and L2 cache, 512kb in the latter case, there's no need for the L3 cache to be that close to the cores. It's still close enough as to not have a huge performance impact and it should make it easier to "recycle" CPU's with broken L3 cache as something else.

It also puts the L3 cache close to the memory controllers, which might actually help speed up overall performance, since cache memory will always be faster than system memory.