We got some additional details about Nehalem generation CPU. We already said that this new one supports DDR3 memory, that it has an integrated memory controller and that it also supports QPI inter chip communication protocol. This is Intel’s answer to Hypertransport.
Nehalem / Bloomfield will need a Tylersburg-DT chipset that will team up with ICH10 Southbridge. All these parts are scheduled for Q4 2008.
The Yorkfield quad core 45 nanometer part will have to suffice until then. As we said months ago there will be a new chipset, X48, to fill the gap, and this one will support FSB 1600.