Published in PC Hardware

AMD 45nm Shanghai to have improved IPC

by on08 May 2008


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Roadmap: Instructions per clock


AMD's Server VP has officially talked about the new server plans and Randy Allen, Corporate Vice President and General Manager for server and workstation market, has said that the upcoming 45nm Shanghai core is still on track for 2H 2008.


We can remind you that Dirk Meyer, the second in charge at AMD, has said that volume production of 45nm quad-cores, including Shanghai, will start in Q4 2008.

The new Shanghai design will feature coherent HyperTransport 3.0 for processor to processor communication. The new 45nm Quad-core will also increase the amount of shared L3 cache from 2MB with current Barcelona design to 6MB with Shanghai, and this new Chinese chip promises instruction per clock (IPC) enhancements.

We were a bit shocked to see that currently there are no any plans for an eight-core Montreal 45nm chip, but again this might be a desktop only chip, or AMD wants to keep this as a little surprise.

Let us just remind you that we wrote about Shanghai’s specs more than a year ago here and we took the picture of the working one here.

Also read

AMD's Shanghai K10.5 has 6 MB L3 cache April 2007

Shanghai 45nm Opteron up close

Last modified on 08 May 2008
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