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Tuesday, 12 July 2011 12:16

Synopsys has 20nm design breakthrough with Samsung

Written by Nick Farell
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Successful tape out
Synopsys announced that it has achieved a critical milestone with the successful tapeout of the first 20 nm test chip based on Samsung’s High-k metal gate (HKMG) process technology. The test chip was implemented using Synopsys’ Galaxy Implementation Platform, including the Design Compiler synthesis, IC Compiler place-and-route, In-Design physical verification with IC Validator, StarRC extraction and PrimeTime signoff tools.

It is the outcome of an early R&D collaboration between Samsung and Synopsys aimed at developing and validating a comprehensive design implementation infrastructure for the next The new ideas will allow fast routing throughput while delivering full compliance with thousands of complex rules and manufacturable routing patterns.

KM Choi, vice president of Infrastructure Design Center System LSI Business at Samsung said his outfit was quickly readying its 20nm solution. Working closely with Synopsys should mean that 20nm gear will be out there soon, he said.


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