Published in Processors

Intel reveals more about Knight’s Landing

by on24 June 2014

None shall pass

Intel unveiled more details on its latest supercomputing chip called “Knight's Landing” as it bangs coconuts on the way to its launch. So far Knights Landing has been standing quietly and all we have known about it is using a 14 nanometer process node and an integrated on-package memory.

However now Chipzilla is saying that the chip will use the Silvermont architecture, can push out up to 3 teraflops of peak performance, and, most importantly, will use the Omni Scale interconnect fabric. Omni Scale is still fairly mysterious, but Intel said it would be a scalable future-proof platform that would support everything from PCIe adapters, edge switches, director systems, to Intel’s own silicon photonics and open software tools.

Intel says that thanks to Omni Scale, the bandwidth bottleneck will be so last year and as out of fashion as shoulder pads. Charles Wuischpard, Intel’s boss of the Workstations and HPC division said that one of the choke points in software is I/O and memory bandwidth, and this is specifically designed to remove that bottleneck.

Knights Landing will have 16GB of stacked memory based on Micron’s Hybrid Memory Cube technology, which uses Through Silicon Via (TSV) technology. This is said to provide five-times the bandwidth of off-chip DDR4. The number of cores on the chip has not yet been revealed, but 72 has been suggested as this is the number of decans in astrology, The atomic number of hafnium, and 72 demons and other spirits in the Goetia The Lesser Key of Solomon.

Knights Landing is expected to start shipping to commercial HPC systems in the second half of 2015. That is if it is not hacked to bits by King Arthur.


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