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Wednesday, 28 March 2007 18:38

TSMC ready with 55 nm

Written by Fuad Abazovic


Image

90 percent linear shrink from 65 nm


TSMC is ready with its half node 55 nanometre process, a 90 percent linear shrink from 65 nanometre. The shrink includes I/O, analogue circuits and the initial test production starts this quarter.


The big fab claims that 55 process delivers significant die cost saving from 65 nm and at the same time offering 10 to 20 percent lower power consumption at the same clock speed. As 55 nanometre is a a direct shrink, the chip companies can leverage existing libraries and port their 65 chips to 55 nanometre. This should not be a big trouble.


It also offers its key customers to use CyberShuttle prototype program that allows multiple customers to share the cost of the single mask set and prototype wafers on the pilot run. This means that Nvidia and ATI can split the bill when they tape out their 55 chips, but we don’t think that this will happen.  You never know.

 

TSMC offers six generation of marchitecture from 350 nanometre gate size to 55 nanometre.


You can read more here.

 

Last modified on Wednesday, 28 March 2007 21:45
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