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Monday, 05 January 2009 15:39

Nvidia's 40nm GT212 to have 384 SPs, 96 TMUs

Written by Fudzilla staff

Image

Half-step between GT200b and GT300


According to
a recent report from Hardware-Infos, the specifications of Nvidia's coming flagship 40nm GT212 architecture have been identified and revealed from unnamed sources near Nvidia, as usual. To start matters off, GT212 is the successor to 55nm GT200b which is currently rolling into production.  In comparison, the upcoming architecture is essentially following two similar footsteps of 65nm G92 last March - a die shrink to a smaller fabrication process and a decrease in memory interface width.

The memory interface of GT212 will decrease from 512-bit on GT200 to 256-bit, which is quite similar to what occurred with AMD's RV770.  To compensate, however, Nvidia will follow suit by incorporating Hynix 7Gbps GDDR5 into its GT212 as well as into the rest of its 40nm lineup.  In addition, the stream processor count of GT212 will increase from 240 in GT200 to 384, and the number of texture mapping units will increase from 80 to 96.

As Nvidia's second-generation unified shader architecture, GT200 features 10 texture/processor clusters. According to analysis, if GT212 follows this structure, it will feature 16 texture/processor clusters and is likely to adopt a third-generation unified shader architecture with 4 shader models and 8 texture mapping units, thus bringing the total shader count to 384 as stated.  In layman's terms, the total stream processor count of GT212 will increase by 60% and the texture mapping units will increase by 20%.

Because of the sharp increase in stream processors, the number of transistors will jump to nearly 1.8 billion, a great 400 million more than GT200.  The new die surface will be just under 300mm² which should significantly reduce manufacturing costs for Nvidia when the company needs it most.  All in all, the complexity of the new architecture will be less than a fifth more than GT200 due to lower PCB complexity needed as a result of the lowered memory interface.

The new architecture is confirmed to launch in Q2, most likely around April or May, although the latter statement has not been confirmed.
Last modified on Monday, 05 January 2009 15:40
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