worked out a new chip-stacking technology which will allow 3D chips and extend the life of Moore’s Law. The technology, dubbed 'through-silicon vias', allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.
3D chip stacking takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another.The compact sandwich of components reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.
The new IBM method eliminates the need for long-metal wires that connect today’s 2-D chips together and rely on through-silicon vias, which are vertical connections etched through the silicon wafer and filled with metal.
It shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.
Sample chips will be available in the second half of 2007 and will go into production in 2008.