Error
  • JUser::_load: Unable to load user with id: 67

Featured Articles

Apple announces its Apple Watch

Apple announces its Apple Watch

Apple has finally unveiled its eagerly awaited smartwatch and surprisingly it has dropped the "i" from the brand, calling it simply…

More...
Skylake 14nm announced

Skylake 14nm announced

Kirk B. Skaugen, Senior Vice President General Manager, PC Client Group has showcased Skylake, Intel’s second generation 14nm architecture.

More...
Apple officially announces 4.7-inch iPhone 6 and 5.5-inch iPhone 6 Plus

Apple officially announces 4.7-inch iPhone 6 and 5.5-inch iPhone 6 Plus

The day has finally come and it appears that most rumors were actually spot on as Apple has now officially unveiled…

More...
CEO: Intel on target for 40m tablets

CEO: Intel on target for 40m tablets

Intel CEO Brian Krzanich just kicked off the IDF 2014 keynote and it started with a phone avatar, some Katy Perry…

More...
Aerocool Dead Silence reviewed

Aerocool Dead Silence reviewed

Aerocool is well known for its gamer cases with aggressive styling. However, the Dead Silence chassis offers consumers a new choice,…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Thursday, 12 April 2007 10:26

IBM Goes 3D with Moore?s Law

Written by

Image

3D chips have 100 times more channels


IBM has worked out a new chip-stacking technology which will allow 3D chips and extend the life of Moore’s Law. The technology, dubbed 'through-silicon vias', allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.
 
3D chip stacking takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another.The compact sandwich of components reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.

The new IBM method eliminates the need for long-metal wires that connect today’s 2-D chips together and rely on through-silicon vias, which are vertical connections etched through the silicon wafer and filled with metal.

It shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2-D chips.

Sample chips will be available in the second half of 2007 and will go into production in 2008.

More here.
Last modified on Thursday, 12 April 2007 10:34
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments