Featured Articles

Intel releases tiny 3G cell modem

Intel releases tiny 3G cell modem

Intel has released a 3G cellular modem with an integrated power amplifier that fits into a 300 mm2 footprint, claiming it…

More...
Braswell 14nm Atom slips to Q2 15

Braswell 14nm Atom slips to Q2 15

It's not all rosy in the house of Intel. It seems that upcoming Atom out-of-order cores might be giving this semiconductor…

More...
TSMC 16nm wafers coming in Q1 2015

TSMC 16nm wafers coming in Q1 2015

TSMC will start producing 16nm wafers in the first quarter of 2015. Sometime in the second quarter production should ramp up…

More...
Skylake-S LGA is 35W to 95W TDP part

Skylake-S LGA is 35W to 95W TDP part

Skylake-S is the ‘tock’ of the Haswell architecture and despite being delayed from the original plan, this desktop part is scheduled…

More...
Aerocool Dead Silence reviewed

Aerocool Dead Silence reviewed

Aerocool is well known for its gamer cases with aggressive styling. However, the Dead Silence chassis offers consumers a new choice,…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Tuesday, 01 May 2012 10:42

Nvidia patents parallelisation of GPU data

Written by Nick Farrell



Keep all your processors hierarchical


Graphics dalek Nvidia has filed for an extension to its patents  for a hierarchical processor array.

It looks like Nvidian thinks that Patent 7,634,637 can be extended to cover some new ideas it has to fix a core design problem  hat results in wide and ineffective graphics rendering pipelines. Nvidia has applied for a patent that describes the idea is that there are two or three tiers of processing cores with dedicated functions. The pipelines would include different shaders, such as a vertex shader unit, a geometry shader, a pixel shader and some others.

In the patent Nvidia says that "each massively parallel stage in a stage-by-stage pipeline tends to provide little granularity of control of portions of each parallel stage. Each "massively parallel stage becomes unwieldy and prohibitively time-consuming to design". As the massively parallel stage struggles during operation to find sufficiently wide units of work to fully occupy the data path its usage is cut back.

Nvida's cunning plan is to keep parallelisation efficient, by using multiple levels of processing hierarchies with multiple classes of graphics operations being associated with a different stage of graphics processing. Each level would include a module that is capable of processing all graphics functions. There would also be one top-level component that is able to distribute certain classes of work to lower level classes of processors.

It also comes out with a third-level class in the processor hierarchy that would be reserved for general purpose computations, and a specialised graphics function module that can perform graphics operations carried out based on frame buffer data.

The result is a design which is configured to execute a large number of threads in parallel.

More here.

Last modified on Friday, 04 May 2012 08:24

Nick Farrell

E-mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments