Featured Articles

TSMC: Volume production of 16nm FinFET in 2H 2015

TSMC: Volume production of 16nm FinFET in 2H 2015

TSMC has announced that it will begin volume production of 16nm FinFET products in the second half of 2015, in late…

More...
AMD misses earnings targets, announces layoffs

AMD misses earnings targets, announces layoffs

AMD has missed earnings targets and is planning a substantial job cuts. The company reported quarterly earnings yesterday and the street is…

More...
Did Google botch the Nexus 6 and Nexus 9?

Did Google botch the Nexus 6 and Nexus 9?

As expected, Google has finally released the eagerly awaited Nexus 6 phablet and its first 64-bit device, the Nexus 9 tablet.

More...
Gainward GTX 970 Phantom previewed

Gainward GTX 970 Phantom previewed

Nvidia has released two new graphics cards based on its latest Maxwell GPU architecture. The Geforce GTX 970 and Geforce GTX…

More...
EVGA GTX 970 SC ACX 2.0 reviewed

EVGA GTX 970 SC ACX 2.0 reviewed

Nvidia has released two new graphics cards based on its latest Maxwell GPU architecture. The Geforce GTX 970 and Geforce GTX…

More...
Frontpage Slideshow | Copyright © 2006-2010 orks, a business unit of Nuevvo Webware Ltd.
Monday, 20 February 2012 16:44

VIA getting into SSD design

Written by Nick Farrell



It is the newest bandwagon to jump on


VIA appears to be thinking that there is money to be made in SSD design.

We got a clue this morning when an outfit called Tensilica sent us a press release saying that VIA has selected Tensilica's Xtensa dataplane processors (DPUs) for a system-on-chip (SOC) design for solid state drives (SSDs). VIA felt that Tensilica's DPUs would provide over four times the performance of competing processors on key algorithms used to benchmark competitive alternatives and went for it.

But what this seems to be telling us is that VIA has worked out that there is shedloads to be made on the back of SSDs Tensilica's DPUs allow designers to customize the IP core, mix both control and signal processing, and add high-bandwidth connectivity to increase performance without increasing the clock speed. For example, designers can use single-cycle bit field manipulation and arithmetic instructions along with multiple simultaneous single-cycle table lookups to achieve over 10 times the efficiency of other processors. This not only increases IOPS, but also significantly reduces the energy consumed and the complexity of the SOC design itself.

Jiin Lai, VIA's CTO is expecting a lot of competition an the SSD market and he thinks there is a significant advantage using Tensilica DPUs to lower the power and increase the throughput of his  products.

Nick Farrell

E-mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
blog comments powered by Disqus

 

Facebook activity

Latest Commented Articles

Recent Comments