As of April 2016, the company has 20 customers already engaged with its 7-nanometer process node, and it expects to have 15 customer tape-outs in 2017. The company just finished taping out its 10-nanometer FinFET process for initial customers sometime last quarter. Some proof of concept 10nm chips were initially shown at the 52nd annual Design Automation Conference, where TSMC displayed a prototype ARM Cortex A57 IC featuring 110 percent more transistors than its 16-nanometer FinFET+ process. DAC 2016 will be held June 5th - 9th in Austin, Texas, and we expect the company will have more to display on its 10-nanometer process and possibly some details on 7-nanometer plans.

"TSMC's 7nm technology leverages 95% the same equipment as 10nm," said Liu, adding that the company is "well on track" with its 7nm development. "N7 is a further extension of N10 technology, with more than 60 percent in logic density gain and 30 to 40 percent reduction in power consumption," Liu indicated.

As we mentioned last Friday, TSMC's revenues declined 18 percent last quarter mainly as a result of slowing high-end smartphone sales. This year, the company expect to spend close to $10 billion on ramping up its 16-nanometer process mode. At the same time, the company has already begun production on its 10-nanometer node at its Fab 12 300mm wafer plant and hopes to open Fab 15 for further 10nm FinFET production later this summer. Meanwhile, R&D engineers are already working on its 7-nanometer process node and plans to begin volume production sometime in 2018.

Company CEO Mark Liu wants to have 7-nanometers on the market by 2018 and 5-nanometers by 2020 using Extreme UltraViolet (EUV) lithography, a method that will expose over 1,000 wafers to EUV lasers in a 24-hour period with a sustained power of over 90 watts.