A physical teardown of Intel’s Panther Lake shows that Chipzilla’s 18A process is competitive, though it hasn’t magically vaulted ahead of TSMC.
NeoTeo pulled apart a Core Ultra 7 365 and examined the transistors, wiring, packaging and individual tiles to see what Intel’s long-delayed manufacturing comeback actually looks like in silicon.
For those not in the know, Panther Lake is Intel’s first commercial processor using RibbonFET gate-all-around transistors and PowerVia backside power delivery. Intel has spent years telling anyone still awake during its manufacturing presentations that those technologies would restore its process credentials. The physical silicon suggests the engineering is real, although the competitive picture is less dramatic than the marketing department might prefer.
NeoTeo found that Intel 18A compute logic has roughly the same logic density as TSMC’s N3E GPU logic. However, Intel 18A does not take the density crown from TSMC N3P, N2 or Samsung SF2. That leaves Intel with a serious modern process, but not the sort of clear manufacturing lead it enjoyed before its infamous 10nm troubles sent its roadmap wandering into the wilderness.
Intel’s RibbonFET design replaces FinFETs with four stacked horizontal silicon nanosheets. The gate surrounds each ribbon, giving better electrostatic control as transistor dimensions shrink.
Samsung’s comparable SF2 MBCFET structure uses three nanosheets in the examples. The number of sheets alone does not determine performance because their width, thickness, materials and electrical characteristics all play a part. PowerVia makes the more substantial architectural change. Conventional chips route power and signals through the metal layers above the transistors, leaving both fighting for increasingly cramped space.
Intel shifts the main power distribution network to the back of the wafer. Power is delivered through backside metal layers and tiny through-silicon connections, while most signal wiring remains on the front. The Panther Lake implementation has frontside metal layers running from M0 to M14 and six backside layers from BM0 to BM5. Nano-TSVs connect the backside supply network to local transistor contacts.
Moving power away from the frontside reduces routing congestion and allows shorter, wider power connections. It can improve voltage delivery and leave designers more room for signal routing, although the manufacturing process becomes considerably more complicated.
Intel previously said 18A could deliver up to 15 per cent better performance per watt and 30 per cent greater chip density than Intel 3. The company put 18A into production during 2025 and is already developing the enhanced 18A-P process.
Panther Lake shows how international modern Intel processors have become, despite the company’s enthusiasm for talking about US manufacturing. Both Panther Lake compute tile variants use Intel 18A. The smaller four-core Xe3 GT1 graphics tile uses Intel 3, while the larger 12-core GT2 graphics tile is manufactured on TSMC N3E. The I/O tiles use TSMC N6.
Intel ties the collection together using its Foveros-S packaging, placing the compute, GPU and I/O tiles on a passive base tile. The teardown found another interesting benefit of the new process at the core level. Panther Lake’s Cougar Cove P-core fits 20 per cent more L2 cache into approximately the same area as the Lion Cove core used in Lunar Lake and Arrow Lake.
Its Darkmont low-power E-core cluster is five per cent smaller than Lunar Lake’s Skymont equivalent, with much of the reduction coming from denser L2 cache regions.
The physical examination gives Chipzilla evidence that its manufacturing roadmap has returned to producing competitive silicon.
What it does not provide is proof that Intel has regained an outright process advantage. Cost, yields, clock speeds, power consumption and the ability to manufacture 18A economically at scale will decide that particular argument.
