Chinese memory maker CXMT plans to launch denser DDR5 server modules before year-end, taking its vertical transistor technology into commercial products.
CXMT president Cao Kanyu outlined the plans at the Integrated Chips and Chiplets Conference on 10 October. The first product using its 4F² technology will be a registered DDR5 memory module, or RDIMM.
According to Tom’s Hardware the design uses Vertical Surrounded Gate transistors, with upright channels surrounded by their gates to improve electrical control and reduce leakage. Standing the transistor vertically helps shrink the memory cell and squeeze more storage into the available space.
A 4F² cell occupies approximately two-thirds the area of a conventional 6F² cell at the same feature size. That represents a theoretical one-third footprint reduction, without requiring the underlying manufacturing dimensions to shrink proportionately.
CXMT has disclosed neither speeds nor capacities for the forthcoming modules, leaving buyers waiting for the numbers that determine practical performance. The density promise is substantial, although a conference announcement remains easier to manufacture than a reliable server DIMM.
Cao said CXMT has more than 300 published patent families associated with its 4F² work, reflecting years of development. The company wants the technology to help it overcome engineering barriers in a server market historically dominated by overseas suppliers.
The wider industry is exploring three-dimensional designs that separate manufacturing processes for memory arrays and their supporting logic. Wafer-level hybrid bonding can connect these sections, letting engineers optimise storage density and logic performance independently.
CXMT published research on the technology in 2021, 2023, and 2025, including an 8Gb full-array example at IEDM 2023.
Its fifth-generation G5 DRAM platform is already in mass production, while the company previously demonstrated DDR5-8000 and LPDDR5X-10667 memory. Those developments give established suppliers increasingly concrete reasons to watch their Chinese competitor.
Samsung presented a 16Gb 4F² design at ISSCC 2026, using vertical-channel transistors and wafer-to-wafer hybrid copper bonding.
South Korean reporting subsequently separated Samsung’s vertical-transistor version into a project called D0a-V, with no firm production timetable disclosed.
