Google is sniffing around Marvell for yet more silicon.
Talks between Google and Marvell have started on two new chips aimed at making AI inference less of a slog.
One chip is a memory processing unit designed to work alongside Google’s Tensor Processing Unit. The other is a new TPU built specifically for running AI models.”
No one is saying how far along the chats are, but the shape of it is clear enough: one bolt-on helper for today’s TPU setup and one fresh TPU design for inference.
The two chips have very different jobs, at least on paper. The first is not a custom TPU at all, but a memory processing unit that sits next to the TPU and tries to take some pressure off the memory subsystem. The MPU offloads some memory operations from the main chip or system and dumps them onto a dedicated block.
The second chip is the proper headline grabber, a next-generation TPU tuned specifically for AI inference models.
Google’s flagship accelerator is its TPU v7, the Ironwood line, with 192 GB of HBM, 4,614 TFLOPs peak and Superpods built from 9,216 chips.
ASICs are being treated like the answer to everything in AI inference, but the supply chain is still the same old mess, with capacity tapped out across the big chipmakers.
There have been reports that demand for Ironwood is picking up, yet production limits do not magically vanish because the hype graph went up and to the right.
The MPU is being framed as a secondary inference accelerator, with the write-up comparing it to “NVIDIA’s Groq 3 LPX”, which is certainly one way to introduce an LPU.
That LPU is described as packing 500 MB of SRAM and pushing 150 TB/s of bandwidth, the sort of numbers that make marketing departments start breathing heavily.
If the plan lands, the next Google TPU paired with an MPU could shove more speed through the memory subsystem for inference workloads.
