Google is reportedly planning a Gemini-tuned TPU that could bypass costly CoWoS packaging by wiring memory directly onto silicon.
With the AI race belting along, big tech is hunting for custom chips that can rival Nvidia’s expensive and hard-to-get GPUs. Google’s Tensor Processing Units and Amazon’s Trainium chips are among the alternatives promising lower power use and cheaper AI compute than Nvidia’s kit.
Now Morgan Stanley claims Google’s new TPU chips will be tailored for its Gemini models and could remove the need for TSMC’s chip-on-wafer-on-substrate packaging.
Google’s packaging choices for TPU chips have become a reliable source of industry gossip.
Several reports have claimed that Google and its TPU design partner, MediaTek, might use Intel’s EMIB-T packaging technology for future TPU chips.
Analysts have been muttering that choice could depend on yield, or whether Intel can deliver working chips without the usual foundry grief. Morgan Stanley now claims Google wants to remove the need for advanced packaging from the design altogether.
Intel’s EMIB-T technology is widely seen as suitable for mid-tier AI chips, while TSMC’s CoWoS remains the favoured option for high-performance parts such as Nvidia’s AI GPUs.
A leaked architecture diagram reportedly shows a system with two TensorCores, each with a VPU and Vmem, connected to HBM3 controllers over PCIe Gen5 x16.
The design is said to include PCIe Gen2 x1, several memory and DMA interconnects, an ICI router and six 200G SerDes octals.
Google appears to be designing a chip called “Frozen V2”, which aims to solve two problems without chucking more money at packaging. The TPU is meant to run Gemini AI models more efficiently by customising the silicon around Google’s own workloads.
Google reportedly wants to hardwire the chip’s SRAM directly into the silicon, eliminating the need for separate packaging technologies such as CoWoS.
Morgan Stanley says Frozen V2 could enter early-stage production next year and ramp production in 2028.
The analysts said Marvell could be one possible partner, though nothing has been confirmed yet.
The idea is not entirely new. AI chipmaker Taalas showed off a similar approach earlier this year. Taalas hardwires neural network weights directly onto silicon to reduce the bottleneck between memory and compute.
The catch is that a new chip may be needed whenever a significantly improved AI model arrives, which sounds fun for nobody outside a procurement spreadsheet. That suggests Google wants more control over the stack, fewer packaging headaches and a better way to stop Nvidia from eating everyone’s lunch.
Google, Gemini, TPU, Frozen V2, Nvidia, TSMC, CoWoS, Marvell, AI chips
