IBM boffins have emerged from their smoke filled labs claiming to have cooked up a transistor-stacking trick that claims sub-1 nanometre performance without actually shrinking reality.
Biggish Blue says its new chip architecture can cram nearly 100 billion transistors onto a chip the size of a human fingernail. That is nearly twice the transistor density of its previous chip technology.
The company calls it the “world’s first sub-1 nanometre chip technology” for AI data centres. This means IBM reckons its nanostack design gives the performance expected from a fantasy chip with features below 1 nanometre.
IBM Research director and IBM Fellow Jay Gambetta told Ars Technica: “It’s not just an incremental step, it’s a meaningful leap forward… pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.”
That sounds grand, although chip node names stopped meaning actual physical dimensions years ago. The 1970s and 1980s were simpler times, when a 180-nanometre node had parts roughly matching the label.
Modern 3-nanometre and 2-nanometre chips do not work like that. IBM’s 0.7-nanometre claim, dressed up as a 7 angstrom node, is more about expected performance than tiny transistor bits violating physics for sport.
The nanostack architecture stacks transistors vertically in a staggered layout, packing more of them into the same area. It builds on IBM’s nanosheet transistors, which paved the way for its 2-nanometre node in 2021.
Each basic nanostack unit uses two transistors stacked and bonded together. Each transistor contains three nanosheets, each 5 nanometres thick, or about 15 rows of silicon atoms.
There is about 9 nanometres between each nanosheet, which rather spoils the “sub-1 nanometre” magic show if you were expecting atoms squeezed into a phone box (that is bigger on the inside than the outside).
IBM claims the architecture could deliver 50 per cent higher computing performance or 70 per cent better energy efficiency than its 2-nanometre chips. The company introduced the design at the 2025 IEEE Symposium on VLSI Technology and Circuits in Kyoto.
IBM boffins said the nanostack architecture can improve static random-access memory scaling by 40 per cent. SRAM matters because AI workloads need fast read and write operations, even if they burn through power like a crypto bro with free electricity.
The gain comes from a staggered-channel design for SRAM bit cells, the six-transistor memory units inside the chip. IBM says this cuts overall cell height by 40 per cent and squeezes more SRAM into the same space.
SRAM scaling has been getting a bit knackered lately. Gambetta said scaling improved by only a few per cent between the 3-nanometre and 2-nanometre chip generations.
“This achievement of 40 per cent will eventually industrialise itself in AI workflows, which require higher bandwidth and high efficiency,” Gambetta said.
IBM has not named partners for commercialising its new sub-1-nanometre node technology. Bu reckons chips using nanostack could enter production within five years at the earliest and probably within a decade.
“It will replace nanosheet as today’s mainstream in leading foundries, whether it’s CPUs or GPUs,” Bu said. “Within a decade, this will become another mainstream that we have invented and helped the industry transform.”
