Biggish Blue has bolted Arm into its big iron without turning its mainframe into a translation circus.
According to Serve the Home IBM used Hot Chips 2026 to show off future IBM Z and LinuxONE processors, alongside an AI inference acceleration chipset built for enterprise jobs that dislike falling over.
IBM distinguished engineer Christian Zoellin walked through a dual-ISA core that can natively run z/Architecture and Arm AArch64. He then covered a second-generation on-chip AI accelerator aimed at chunkier enterprise inference workloads. Big Blue opened with the usual mainframe history lesson, dragging Z from out-of-order execution and 64-bit Linux through pervasive encryption, post-quantum security and now AI.
The pitch is that Z remains the reliability bunker, while IBM bolts on modern software ecosystems without losing the stuff banks still trust with their cash pipes. IBM claims about 70 per cent of the world’s transaction volume runs across IBM Z mainframes. By dragging in the Arm ecosystem, it reckons a new class of applications can land on Z without too much faffing about.
The main event is a mainframe-grade dual-ISA processor with 11 IBM Z cores running at more than 5.7GHz on a 2nm process. Each core can execute both z/Architecture and AArch64 natively, which is a bit mad even by big iron standards.
IBM pairs those cores with 36MB private L2 caches, stitched into virtual L3 and L4 caches. There is a dedicated on-chip DPU for I/O acceleration, plus blocks for AI, compression, cryptography and sort. The design is SMT=2 and has a 432 MB virtual L3 cache and a 3.5GB virtual L4 cache. Those specs were shown live rather than stuck on the slide deck.
IBM has implemented AArch64 in hardware rather than shoving it through translation. That means little-endian Arm sits beside big-endian z/Architecture, with AArch64 v9.3, SVE and SVE2 support. The core implements 2,792 AArch64 instructions and IBM claims Arm SystemReady compliance. In normal language, Arm software should see a proper Arm processor, not a mainframe wearing a silly hat.
Arm software runs unmodified, out of the box and on a standard Arm platform. IBM said those 2,792 AArch64 instructions are more than twice the number of Z instructions. IBM made a gag about “reduced” RISC, which is probably the sort of thing that gets a laugh at Hot Chips.
Branch prediction shows how much of the existing Z core design IBM reused for AArch64. Automation consumes Arm’s XML architecture descriptions to feed decode, while dispatch and issue repurpose register rename for the GR16-31 range.
IBM calls out a new control for SVE, new dataflows for FP16, Bfloat16, and crypto, plus less-obvious CISC reuse such as memory copy. This is Z and Arm living inside one core, which is the sort of engineering trick that makes cloudy commodity kit look a bit beige.
On the software side, IBM exposes Z accelerators as platform devices to Linux on Arm. Crypto, GZIP compression, and the on-chip AI unit appear as Linux devices with latency comparable to that of native Z instructions. The Z ISA can still expose them as instructions for s390x workloads.
Big Blue is aiming at 99.999999 per cent availability. It cites error checking across arrays, dataflows and control, transparent recovery from transient faults, core sparing for persistent faults, concurrent repair and RAIM memory protection.
Nvidia has been doing similar reliability work by replacing many cables with PCBs in its systems, but IBM’s big-iron obsession still lives in a different bunker. Rather than forcing one software world, IBM wants Z and Arm to coexist through Linux KVM and OpenShift Virtualisation.
The platform maps s390x Linux and Arm64 Linux alongside IBM z/OS, with logical partitions sharing the same processor. A thread can run either s390x or Arm software, and the switch takes nanoseconds. The point is to let Z customers keep their mainframe code while tapping the broader Arm software base.
IBM’s second-generation AI inference accelerator is built for larger enterprise workloads. The chip packs 16 active AI cores and one redundant core, which means even the AI bit gets a spare tyre. It supports the FP4 and MXFP4 data types, which IBM says can deliver up to four times the TOPS.
It adds 96GB of HBM3e memory running at up to 4TB/s, roughly 20 times the memory bandwidth of the current generation. PCIe Gen6 acts as a low-latency peer-to-peer interface. IBM is pitching the part for mission-critical AI, because apparently hallucinating chatbots now need confidential computing and mainframe-grade uptime.
The security stack protects data and models at rest, in transit and in use, including quantum-safe cryptography. Secure boot and on-chip cryptography sit beside firmware tuned for availability, serviceability and tight integration with IBM Z.
