Intel wants a new memory stunt for the AI land grab, and it is pitching Z-Angle Memory as the thing that makes HBM look tired.
Z-Angle Memory, or ZAM, is being cooked up with SoftBank and is meant to be a low-power, high-density alternative to HBM for serious bandwidth and capacity.
Fresh details suggest ZAM is targeting twice the bandwidth of HBM4 and it is meant to nip at HBM4E too, even though it is a 2028 to 2030 play.
At VLSI Symposium 2026, Chipzilla and SoftBank subsidiary SAIMEMORY are set to spill more, after previewing a chunky 3D DRAM architecture.
The demo stack is a nine-layer design, built from eight DRAM stacks separated by a three-micron silicon substrate, with a single logic controller sitting on the main substrate.
The interconnect is split across three TSV layers, each packing about 13.7k through-silicon vias using hybrid bonding, because nothing says “simple” like a microscopic pin cushion.
Capacity is pegged at 1.125GB per layer, which works out at roughly 10GB per stack and 30GB for the whole package.
The ZAM stack measures 171mm², or 15.4 x 11.1mm, and is claimed to deliver 0.25 Tb/s/mm² bandwidth density, translating to 5.3 TB/s per stack.
HBM is the current darling for AI accelerators and GPUs, but scaling it tends to drag heat and power along for the ride.
ZAM’s pitch is a vertical structure that dumps heat more cleanly because it does not need to shove everything through the same wiring layers.
Chipzilla says the design is geared for high density, wide bandwidth and lower transfer power, with ultra-thin silicon slices and via-in-one TSV tricks to stack beyond nine layers.
It relies on magnetic-field-coupled wireless I/O and fancier bonding so the stack can scale without the usual packaging tantrums.
The endgame is a dense 3D memory block in 3.5D packaging, combining vertical and horizontal layers on one substrate with power and ground rails, silicon photonics and legacy I/O.
If the first live demo matches the slide, HBM’s comfy monopoly might start feeling a draught.
