Meta is not binning its custom silicon plans any time soon and has effectively “doubled down” on its ASIC push, according to the company blog.
The outfit has joined hyperscalers who want to diversify away from Nvidia as infrastructure buildout costs get silly. Google and Amazon are held up as proof that “fruitful” ASIC programmes happen when you tune chips for in-house workloads.
Meta says its MTIA roadmap is on track, and it is moving at a pace that looks borderline reckless. It claims it will deploy “four” new chips in the MTIA family within the next two years; each aimed at a specific workload from training to GenAI inference.
MTIA 300 is framed as the starting point, built mainly for ranking and recommendation training. Meta ties that to a 200 GB/s scale-out network, plus a design with one compute chiplet and two network chiplets.
The company says MTIA 300 pairs that with several HBM stacks delivering 216 GB of capacity and 6.12 TB/s of bandwidth. Meta reckons this laid the groundwork for MTIA 400, which it describes as far more competitive.
MTIA 400 shifts to a more general workload focus, with a module TDP of 1200 W and HBM bandwidth quoted at 9.2 TB/s. HBM capacity rises to 288 GB, with performance figures of 12 PFLOPs for MX4 and six PFLOPs for FP8 or MX8.
For BF16, MTIA 400 is listed at three PFLOPs, and Meta pegs its scale-up domain size at 72. It claims a 1.2 TB/s scale-up network and a 100 GB/s scale-out network, which is a step down from MTIA 300’s 200 GB/s.
Meta says MTIA 400 delivers 400 per cent higher FP8 FLOPS and 51 per cent higher HBM bandwidth than the previous generation. It talks up a 72-chip scale-up configuration connected via a switched backplane, with this generation already heading towards deployment.
The more interesting parts are MTIA 450 and MTIA 500, because they go straight for GenAI inference. MTIA 450 is listed with a 1400 W module TDP, 18.4 TB/s of HBM bandwidth and 288 GB of HBM capacity.
Meta quotes MTIA 450 at 21 PFLOPs for MX4, seven PFLOPs for FP8 or MX8 and 3.5 PFLOPs for BF16. The scale-up domain size remains at 72, with 1.2 TB/s of scale-up bandwidth and 100 GB/s of scale-out.
MTIA 500 pushes the inference obsession harder, with a 1700 W module TDP and HBM bandwidth jumping to 27.6 TB/s. HBM capacity goes to 384 to 512 GB, which is the sort of number you quote when you are tired of being memory-starved.
Meta lists MTIA 500 at 30 PFLOPs for MX4, 10 PFLOPs for FP8 or MX8 and five PFLOPs for BF16. Network figures remain flat at 1.2 TB/s for scale-up and 100 GB/s for scale-out, with the same 72-chip scale-up domain.
Meta claims it can keep pace with “commercially available” kit by running a high-velocity cadence. It says chiplet modularity lets it swap individual chiplets each generation, so it does not have to rip up the whole platform every time.
That modular approach is meant to make the fast cycle possible without constant infrastructure surgery. Meta frames MTIA 450 and 500 as inference-first plays that diversify beyond what a standard GPU offers.
There have been whispers that Meta’s latest deal with NVIDIA might mean it will ditch custom silicon, but Meta’s blog post reads like a company backing its own engineers. Meta says these generations will be deployed by 2026 or 2027 to help it squeeze past the compute bottleneck.
