Meta is digging DDR4 out of dead servers to dodge the RAM tax without buying shiny new memory.
The social notworking giant has found a use for old DDR4 memory pulled from decommissioned servers. Instead of binning the modules and ordering expensive new DRAM, Meta is recycling them through Compute Express Link technology.
According to TechRadar CXL lets retired DDR4 memory sit alongside newer DDR5 memory pools on the same machine.
Researchers describe this witchcraft as near-zero-cost memory expansion. Meta says the scheme reduces electronic waste and cuts infrastructure emissions.
Cloud outfits that once treated old memory as junk are now eyeing it like lost treasure. Meta boffins said existing CXL implementations had a problem. Expanded memory delivered nearly 10 times lower bandwidth than local memory and roughly 60 per cent higher latency.
Commercial CXL products made things worse by bundling controllers with DRAM modules.
That stopped companies from reusing large inventories of old DDR4 at scale, which rather defeats the point of recycling the stuff. Meta answered with an internal ASIC called Vistara.
The chip is designed around low latency, power efficiency and recycled memory use. Its software stack works out the right mix of local and expanded memory for each workload. It can switch off expanded memory where the delay would turn savings into a self-inflicted outage.
Meta said: “We address these challenges via hardware–software co-design. On the hardware side, we design an in-house CXL ASIC, Vistara, optimised for DRAM reuse, power efficiency, and low latency.”
“On the software side, we build an optimised solution based on TPP (Transparent Page Placement), determine the appropriate local-to-expanded memory ratio for each workload, and automate per-workload configuration, including disabling expanded memory for workloads that cannot tolerate the increased latency,” Meta said.
Meta claims the architecture is useful enough for production environments handling mixed workloads.
Disaggregated machine-learning inference workloads cut server counts by up to 25 per cent. Distributed cache systems recorded average latency reductions of about 29 per cent, despite relying partly on slower recycled memory.
The results suggest that extra capacity can beat raw memory speed when an application is choking on shortages. The same interconnect technology is drawing attention from chip firms building large accelerator fabrics.
The wider ecosystem includes alternatives to proprietary interconnects such as Nvidia’s NVLink. One of them is Ultra Accelerator Link, or UAL, backed by AMD, AWS, Google, Microsoft and Meta.
