Micron plans to skip a generation of NAND flash, promising denser chips and faster storage as it pushes towards more than 400 layers.
The company intends to move from its current ninth-generation technology, G9, directly to G11. Production is scheduled to ramp during the second half of 2027.
According to Blocks & Files, Micron outlined the changes during its technology and product webinar on 21 October. Its current G9 NAND uses 276 layers and first appeared in the Micron 2650 client SSD in July 2024.
Micron president and chief technology and products officer Scott DeBoer said the jump reflects substantial changes aimed at future AI products. Apparently, even NAND generation numbers are being recruited into the AI sales department.
Compared with G9, Micron claims G11 will double bit density, increase input/output speeds by up to 50 per cent and reduce the energy required to transfer each bit by 25 per cent.
DeBoer said: “This G11 technology is the world’s most advanced NAND. It will ramp in the second half of next year.”
The design uses wafer-on-wafer bonding, and Micron promises more technical details closer to launch. For now, the density, speed and efficiency improvements remain company claims.
Micron outlined two approaches to future storage aimed at demanding AI workloads. One prioritises high input/output operations per second, while the other seeks greater bandwidth through stacked NAND positioned close to an accelerator.
The high-IOPS approach uses single-level cell NAND and smaller blocks. Micron discussed performance targets ranging from 25 million to 100 million IOPS, alongside future SSD capacities reaching 512TB.
Those figures describe its future storage ambitions. Micron has not yet established that a single shipping drive will combine the maximum capacity and performance numbers.
The second approach stacks NAND layers above a base die and connects them through silicon vias. This resembles the vertical connections used in high-bandwidth memory, although NAND serves a different role in the system.
Micron wants storage close enough to the processor to benefit from faster connections, without using the same valuable space beside the accelerator as HBM.
DeBoer said the high-bandwidth NAND would avoid the accelerator’s immediate perimeter, “as we don’t think that has merit, but along closer positioning points to the compute itself to make use of this high performance NAND and the viability of that path.”
The approach puts Micron in territory SanDisk and SK Hynix are exploring with high-bandwidth flash. Their designs similarly stack NAND above a logic or controller die and connect it to a nearby accelerator.
Micron envisages its future AI-focused NAND reaching PCs, workstations, vehicles, robots, mobile devices and wearables.
