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Nova Lake’s compute tile looks leaner than expected

A fresh leak puts Intel’s next Nova Lake tile just under 100 mm², with cache-heavy variants ballooning fast.

Troubled Chipzilla’s Nova Lake rumour mill is coughing up numbers that look annoyingly plausible. A leak pinned on Golden Pig Upgrade says earlier estimates for Nova Lake’s compute tile were mostly on the money.

The leaker claims the standard Nova Lake compute tile measures 14.8 mm x 6.6 mm, which works out at about 97.68 mm². That is just less than 100 mm² for an 8+16 core setup using Coyote Cove performance cores and Arctic Wolf efficient cores, with an extra four low-power E cores that are not meant for overclocking.

That footprint appears chunkier but is still slimmer than Arrow Lake’s compute tile, which is reported to be 117.2 mm². If those figures hold up, Chipzilla is looking at roughly a 16.7 per cent die size reduction, which is not bad for a node hop and a rejig.

None of this is official, so treat it like pub maths until Chipzilla says otherwise. Still, the bigger story is the cache-stuffed variants, because the bLLC version is tipped to stretch to 14.8 mm x 10.4 mm, or about 153.92 mm², roughly 57 per cent larger than the standard tile.

Those bLLC parts are reportedly aimed at AMD’s X3D-style gaming wins, where extra last-level cache can help feed cores without as much waiting around. The catch is obvious: a much larger die on a leading-edge node like TSMC N2 will cost more.

Things get even sillier when you stack tiles, because leaks also point to dual 8+16 compute tile SKUs and a claimed PL4 limit of more than 800 watts, which sounds like the sort of number you put in a leak to watch people argue. In that setup, two standard tiles would land at around 195 mm², while two bLLC tiles would push to roughly 307 mm², which is a lot of silicon to bet on a gaming narrative.

On the AMD side, the comparison floating around puts Zen 5’s eight-core CCD with 32 MB or 64 MB X3D cache at roughly 71 mm², with a rumoured Zen 6 12-core CCD around 76 mm² depending on cache. That gap is exactly why Intel is allegedly throwing cache at the problem.

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