While Nvidia has apparently decided that “good enough” is for the riff raff, the dark satanic rumour has manufactured a hell-on-earth yarn claiming its Vera Rubin platform is getting a memory bandwidth bump for hyperscalers.
Vera Rubin is already being pitched as a full-stack AI infrastructure play, with revamped GPUs, CPUs and networking chips aimed at agentic and inference workloads. Recent reports claim Nvidia has reshuffled key elements, framed as a response to AMD’s push with Instinct MI455X.
SemiAnalysis claims the Vera Rubin NVL72 spec will have 22.2 TB/s of memory bandwidth. That is a hefty leap from the numbers Nvidia showed off at GTC 2025, and it looks like a deliberate move to keep its lead in hyperscaler adoption.
The jump from roughly 13 TB/s to 22.2 TB/s does not come from fairy dust. The claim is that Nvidia is pushing HBM4 beyond standard JEDEC ratings, asking suppliers to raise pin speeds up to 11 Gbps.
Nvidia is working with a narrower eight-stack interface, so squeezing more out of pin speeds is the obvious lever to pull. AMD previously looked comfortable, leaning on 12-Hi HBM4 stacks to claim a 19.6 TB/s figure.
AMD has been talking up the Instinct MI400 family for a while, and it clearly fancies a more serious run at hyperscaler sockets this round. This all seems Nvidia’s attempt to counter this.
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