Samsung and SK hynix are taking different bets on next-generation DRAM as AI turns memory into a knife fight.
Industry insiders claim the Korean memory giants are taking separate routes to make next-generation DRAM chips, as AI data centre buildouts squeeze the memory market.
Demand for AI computing kit has tightened supplies of HBM, DRAM and other chips because they rely on many of the same raw materials.
Samsung is said to be looking at gate-all-around FET, or GAAFET, fabrication technology for its next-generation DRAM chips.
Samsung wants to apply NAND manufacturing tricks to DRAM production, according to the report.
Memory chip production uses a different naming system from application processors, which are usually branded in nanometres. Memory nodes use alphabet soup codes, with 1c referring to chips made at the 10nm node or smaller.
DRAM chips are harder to shrink because they must store data, not just shuffle it around like a processor. Their fabrication needs a capacitor to hold data, working alongside a transistor.
As node sizes shrink, storing data in that capacitor becomes trickier because the capacitor still needs enough capacity to function properly.
That is pushing chipmakers towards 3D DRAM, in which transistors are laid out horizontally rather than stacked vertically. Advances in manufacturing can increase density, but they also raise the risk of transistors getting too close together.
One approach Samsung is developing uses GAAFET manufacturing process technology. In application processor fabrication, GAAFET wraps a transistor gate around its channel.
The gate controls current flow in a transistor, increasing contact with the channel and improving performance, which is why chipmakers have been fussing over the technology.
But DRAM chips include capacitors, so Samsung has to squeeze a GAAFET transistor and a capacitor inside a DRAM cell without creating a tiny silicon dog’s breakfast.
One method under consideration places the chip circuitry for read and write operations under the memory array, similar to NAND chips.
SK hynix is taking another punt with the 4F² approach, where transistors are stacked vertically with gate material wrapped around them.
That sounds close to GAAFET, but the parts that receive data from the capacitor sit under the transistor pillar.
Sources claim SK hynix and Samsung are racing to get their chosen method recognised first, hoping to turn it into the standard model for next-generation DRAM.
