Samsung says HBM5 will double HBM4E performance while cutting heat headaches for the next wave of AI accelerators.
According to Newspim, Samsung Electronics memory product planning corporate vice-president Jangseok Choi revealed the targets at SEMICON Taiwan 2026.
Choi said HBM5 is aimed at achieving twice the performance of HBM4E, with 20 per cent better performance per watt.
For those not in the know, HBM5 keeps the familiar HBM approach, with stacked DRAM sitting beside the accelerator and talking to it through a nearby base die.
Samsung is moving that HBM5 base die to its in-house 2nm process, after using 4nm for HBM4 and HBM4E. The company is preparing 12-, 16-, and 20-layer DRAM stacks for HBM5, with mass production expected around 2028.
Samsung’s zHBM is a more radical design because it places stacked memory directly atop the processor rather than alongside it. That vertical layout is meant to shorten the distance data travels, which should lift bandwidth and reduce the power wasted moving bits around.
The zHBM design targets eight times HBM4E performance, three times better performance per watt, and a 75 to 90 per cent cut in thermal resistance. Samsung’s zNAND-O is aimed at sampling in 2028, offering DRAM-like speed with NAND-like capacity for generative AI and large language models.
Choi described Samsung’s CUBE strategy as focusing on capacity, utilisation, bandwidth and efficiency, with more vertical memory layouts and shorter die-to-die paths.
