Intel has taken the wraps off its Xeon 6+ “Clearwater Forest” server chip, and it is packing up to 288 cores for the data-centre grind.
It is built on the Intel 18A process and relies on Foveros Direct packaging, with Chipzilla pitching it to telecoms, cloud, and edge-AI jobs that thrive on brute parallelism.
Tom’s Hardware Intel’s Xeon 6+ processors with up to 288 cores combine 12 compute chiplets, each containing 24 energy-efficient Darkmont cores per tile, produced using 18A manufacturing technology, two I/O tiles made on the Intel 7 production node, and three active base tiles made on the Intel 3 fabrication process. The compute tiles are stacked on top of the base dies using Intel’s Foveros Direct 3D technology, whereas lateral connections are enabled by Intel’s EMIB bridges.
Troubled Chipzilla is framing Darkmont as an efficiency-core glow-up, with more front-end width and deeper out-of-order machinery to keep threads busy instead of twiddling their thumbs.
Intel’s ‘Darkmont’ efficiency cores have received rather meaningful microarchitectural upgrades. Each core integrates a 64 KB L1 instruction cache, a broader fetch-and-decode pipeline, and a deeper out-of-order engine capable of tracking more in-flight operations. The number of execution ports has also been increased to improve both scalar and vector throughput under heavily threaded server workloads.
The cache story is just as loud, since Clearwater Forest groups cores in fours with shared L2, then piles up more than 1 GB of last-level cache to cut memory trips.
From a cache-hierarchy standpoint, the design groups cores into four-core blocks that share approximately 4 MB of L2 cache per block. As a result, the aggregate last-level cache across the full package exceeds 1 GB, totalling roughly 1,152 MB.
This unusually large pool is intended to keep data close to hundreds of active cores and reduce dependence on external memory bandwidth, thereby increasing performance and lowering power consumption.
Platform-wise, the processor remains drop-in compatible with the current Xeon server socket, with 12 memory channels supporting DDR5-8000 and 96 PCIe 5.0 lanes, 64 of which support CXL 2.0.
If the drop-in socket promise holds while 18A and Foveros Direct behave themselves, Chipzilla will have many cores ready to be shouted at by telcos and hyperscalers.
