A fresh LLVM patch for gfx1310, AMD’s RDNA 5 graphics architecture, points to “Dual Issue” being pushed harder to allow two ops to land in one clock cycle.
The big idea is to broaden the instruction support, loosen the rules and suddenly the silicon can chew through more maths without twiddling its thumbs.
Dual Issue has existed since RDNA 3, yet in the real world it was more of a spec-sheet ornament than something most gamers ever felt.
According to Coelacanth’s Dream: “Dual Issue VALU is a feature implemented in the RDNA 3 architecture (GFX11) that allows simultaneous issuance of up to two types VOPDof system instructions ( ) to both the X and Y sides. However, the number of supported instructions is limited, and some instructions can only be selected on the Y side. There are also several conditions, such as the fact that it is only supported in Wave32 mode and that separate register banks must be used for the X and Y sides to avoid register bank conflicts.V_DUAL_”
They followed up with, “RDNA 5 (gfx1310)VOPD added instructions such as V_{MAX,MIN}_I32_e32, V_SUB_U32_e32, V_LSHRREV_B32_e32, V_ASHRREV_I32_e32extracting the maximum and minimum values of integers, subtraction instructions, and bit shift instructions. On the other hand, bitwise AND instructions V_AND_B32were removed.”
Adding everyday integer ops and shifts is how you stop dual issue being trapped in a narrow little lane.
RDNA 5 is meant to relax some of the old constraints, including allowing the same input register to be used on both sides, which should reduce pointless conflicts.
Coelacanth’s Dream added: “RDNA 5 (gfx1310) has partially relaxed the limitations in Dual Issue, allowing the same input register to be specified for both the X and Y sides, which will also help increase the number of cases in which Dual Issue can be used.”
AMD’s earlier implementation was stuck on requiring Wave32 mode and a fussy register-banking setup, so many workloads never got near the theoretical gains.
Sony is a handy case study in how that can go wrong, since it reportedly binned dual-issue support for the PlayStation 5 Pro because devs couldn’t reliably tap it.
The same rumour mill now claims RDNA 5 is lined up for the PlayStation 6 and Xbox Project Helix, and console buy-in is the only thing that makes this more than lab trivia.
If consoles ship with it, developers get nudged into optimising for it, because console engines and tooling have a habit of dragging the PC world along behind them.
Until RDNA 5 hardware lands and driver stacks behave, this is still a compiler-side hint rather than proof of a smooth real-world uplift.
AMD is sprinkling extra branding on top, promising Neural Arrays for AI, Radiance Cores for ray tracing and “Universal Compression” for memory efficiency, because marketing never met a name it could not inflate.
The patch makes RDNA 5 look less like a paper upgrade and more like a shove towards higher utilisation, yet it still needs software to stop getting in the way.
