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First-silicon success falls off a cliff

Only five per cent of IC and ASIC projects are reaching first-silicon success, suggesting modern chip verification is becoming painfully unforgiving.

The figure comes from the 2026 Siemens EDA and Wilson Research Group Functional Verification Study. In 2024, 14.4 per cent of respondents reported first-silicon success.

According to Semiconductor Engineering, historically, the industry did considerably better. Earlier Siemens research put first-silicon success at roughly 30 per cent for many years, making the latest five per cent figure particularly grim for anyone paying for respins.

Siemens chief scientist for verification Harry Foster said no single culprit was responsible. Larger designs, shortages of verification engineers, schedule pressure and inadequate automation might contribute, but the study suggests the problem has changed more fundamentally.

Modern chips are increasingly software-driven, heterogeneous systems packed with CPUs, GPUs, AI accelerators and embedded processors. Verification therefore must handle interactions that stretch far beyond traditional RTL logic.

The list of things that can wreck a design has grown accordingly. Functional errors remain important, but firmware, power, clocking, timing, safety and security problems can now send expensive silicon heading for another spin.

Testing whether the logic works is no longer sufficient when software, security features, power management and multiple processing architectures must behave properly together.

Design-for-test is becoming more closely tied to functional verification, while safety and security concerns are increasingly intertwined. The tidy boundaries between engineering disciplines are becoming harder to find.

AI and machine learning are entering the verification process as well. Engineers are applying them to test generation, coverage analysis, debugging, regression optimisation and formal verification in an attempt to keep the growing problem vaguely manageable.

Foster cautioned against treating any single trend as the cause of declining first-silicon success. The study does not establish that processor content, AI acceleration, safety requirements or any other individual factor is responsible.

Instead, several changes appear to be happening simultaneously. Foster described the central finding simply: “Complexity has changed.” 

The study suggests verification is shifting from checking individual designs towards establishing confidence in entire software-driven silicon systems. With only five per cent getting the first spin right, the industry has plenty of expensive evidence that its old assumptions are running out of road.

 

TOPICS:
ASIC  ·  chip design  ·  first silicon  ·  functional verification  ·  ic design  ·  semiconductors  ·  siemens eda  ·  silicon verification  ·  verification

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