AMD is releasing its first SoCs with on-package memory, using Versal Gen 2 to promise a 10x compute uplift.
The new Versal Premium Gen 2 Memory on Package adaptive SoCs ditch HBM for LPDDR5X.
The entire tech industry is stuck in a DRAM squeeze, while HBM prices are spiralling like a crypto bro’s weekend budget. AMD’s answer is to put LPDDR5X memory on the package itself, avoiding board-level memory design faff. Versal Gen 2 can carry up to four
LPDDR5X ICs. That gives it up to 32GB of capacity and speeds of up to 9,000MT/s.
The result is up to 288GB/s of bandwidth, which should keep AI inference, video processing and network security workloads moving.
AMD says the Memory on Package design cuts board area by more than 60 per cent. It claims the parts will have a lifecycle of more than 15 years, which is practically geological time in chip marketing.
The move to MoP is partly driven by shortages. It could nudge future mainstream SoCs towards on-package memory, especially if external memory prices keep behaving like airport sandwiches.
The last high-profile x86 example was Intel’s Lunar Lake. Chipzilla used on-package memory there, although AMD’s Versal line is based on Arm IP rather than x86.
AMD said the MoP architecture integrates up to 32GB of LPDDR5X into a single package. It delivers up to 288GB/s of bandwidth in up to 60 per cent less board area, the company said.
That means engineers can build high-bandwidth systems without the risk and time of designing memory at board level.
AMD wants to sell performance without making hardware teams wrestle with another memory layout problem. The design should help compact PCIe, PXI and VPX systems fit in tighter spaces and thermal limits.
By moving memory onto the package, AMD is targeting deployments where discrete memory is too bulky, too hot or too annoying. The company says the approach opens the door to form factors that were difficult or impractical with external memory. Those include Enterprise and Datacentre Standard Form Factor systems and 3U VPX designs. AMD said the setup should help designers meet telecom and VPX requirements that discrete memory approaches often struggle with.
Versal Premium Gen 2 MoP devices integrate CXL 3.1 and PCIe 6.0 at 64Gb/s in hard IP. Paired with AMD Epyc CPUs, the parts are designed to accelerate data-intensive applications.
The company says architects can scale memory resources through LPDDR5X support up to 9,000 Mb/s. They can tie that into CXL memory pooling and expansion modules.
