Google may tap Intel for its next-generation TPU chips, but packaging yields could decide whether the plan survives contact with reality.
The dark satanic rumour mill has manufactured a hell-on-earth yarn claiming that Google is interested in using Intel for its next-generation tensor processing unit chips.
Well-known analyst Ming-Chi Kuo has weighed in on the matter, saying yields will be a key factor in Google’s decision. This is because the search outfit has started focusing on cost savings for the Humufish next-generation TPU design.
For those not in the know, Chipzilla’s EMIB-T packaging technology stands for Embedded Multi-die Interconnect Bridge Through Silicon Vias.
The technology uses a bridge embedded in the organic package substrate. Typical chip packaging uses a silicon interposer to transfer signals between the chip on top and the board below.
EMIB is meant to cut costs compared with interposer-based packaging and support larger chip packages. EMIB-T is a variant that improves conductivity by moving current through Through Silicon Vias.
TSVs are vertical interconnects that connect the chip on top directly to the package on the board below. That gets around traditional EMIB’s limitation, where current has to travel around the bridge like it is stuck in corporate procurement.
Kuo said Chipzilla’s 90 per cent EMIB-T yield is a positive signal, but it needs close watching. Intel has set a 98 per cent yield benchmark for the technology. That figure comes from Flip Chip Ball Grid Array production benchmarks, because EMIB is an extension of FCBGA.
Kuo said moving from a 90 per cent yield to 98 per cent is far harder than getting from zero to 90 per cent. He said the 90 per cent yield is a validation figure rather than a production figure. Google will care about these yields because it needs to compete with Nvidia by cutting costs.
That has led Google to ask TSMC about cost savings if it directly tapes out Humufish’s main design. The alternative would be relying on its partner MediaTek.
A tape-out is the final chip design stage, when completed blueprints are sent to the fabrication outfit for production.
