Intel has started showing off 18A-P, a process node it hopes will make its foundry pitch harder to ignore.
The company has been trying to bring its foundry operation up to scratch by accelerating the development of advanced process nodes and packaging. Its progress with 18A and future nodes such as 14A has created some buzz, but customers still need convincing.
Chipzilla is not rushing everything out the door just to look busy. Instead, it is pushing 18A-P as a customer-friendly node built on the foundations of its 18A process.
At VLSI 2026, Intel said 18A-P is now in risk production. The company claims it brings new features, including Power Boost, which sounds like a gym supplement but is actually transistor plumbing.
Chipzilla says 18A-P delivers nine per cent higher performance at the same power, or 18 per cent lower power at the same performance, compared with 18A. That is based on a standard Arm core sub-block.
The node uses the same gate-all-around and backside power foundations as 18A. It is fully design-rule compatible with 18A, which should let customers reuse existing IP and design flows without binning half their work.
Intel reckons 18A-P’s low-voltage gains make it useful for energy-efficient AI, high-performance computing and emerging compute designs. It adds material changes that can improve thermal resistance by 20 to 40 per cent when used with enhanced EDA workflows.
Chipzilla claims a 10-30 per cent improvement in through-silicon via resistance. It has added PMOS strain engineering to improve mobility, new low-power and high-performance transistor options and a fifth logic Vt pair between ULVT and LVT.
The big new toy is Power Boost, which Intel calls the industry’s first dual-contact architecture enabled by PowerVia backside power delivery for both NMOS and PMOS transistors. The idea is to increase drive current and frequency at matched capacitance for power-constrained chips.
Backside power delivery shifts major power routing to the rear of the wafer. That cuts frontside congestion, shortens wires, reduces vias and gives Intel an 11 per cent area reduction to wave at potential customers.
Intel says 18A-P continues to use backside power with 32nm metal processes, making designs cheaper and reducing manufacturing steps. It supports 160nm and 180nm high transistor cells, with a contacted poly pitch of 50nm.
Chipzilla also used VLSI 2026 to show off research beyond 18A-P. Its foundry engineers, working with the University of California, San Diego, built efficient multi-thousand-gate digital control circuits using hybrid GaN nMOS and silicon pMOS on a 300mm process.
The team claimed a record power-delay product of 6.2 attojoules per stage, more than 1,000 times more efficient than earlier GaN logic approaches. Intel said it was the largest-scale integrated logic on GaN shown to date.
Chipzilla talked up CFET 3D transistors at a 45nm gate pitch and subtractive ruthenium interconnects with an air gap. The latter delivered roughly two per cent better circuit performance than copper interconnects at matched leakage, helped by capacitance cuts of up to 35 per cent.
At Computex 2026, Intel said Diamond Rapids, its next-generation Xeon CPUs, will use 18A-P. That gives Chipzilla a handy internal proof point as it tries to persuade outsiders that its foundry comeback is more than a slide deck.
Reports have linked Intel Foundry with customers including TeraFab, SpaceX and the Fruity Cargo Cult Apple. Nvidia, Google and others are expected to use Chipzilla in some form as the AI supply crunch keeps making capacity look like gold dust.
