Processor startup Nuvacore is developing a CPU core without committing to Arm, x86 or RISC-V, potentially turning conventional chip design on its head.
According to Tom’s Hardware, the company, founded by former Apple and Nvidia architects Gerard Williams III, John Bruno and Ram Srinivasan, has revealed its unusual Core First development strategy. Its first processor design, codenamed WarpCore, aims to separate much of the underlying microarchitecture from the instruction set architecture (ISA).
Traditionally, chip designers choose an ISA before developing their processor, allowing its requirements to shape the rest of the architecture. Nuvacore reckons that modern CPU designs offer enough separation between instruction decoding and execution to postpone that decision.
Modern high-performance processors already translate instructions into internal micro-operations, allowing much of the execution machinery to operate independently of the original instruction format. However, instruction decoding, register handling, memory ordering and software compatibility still impose architectural requirements.
Nuvacore plans to develop much of its foundational CPU intellectual property before deciding which instruction set to support. This approach could let it reuse common execution components across architectures rather than designing everything around a particular ISA from the outset.
The startup’s founders have considerable experience in the processor business. Williams previously worked on Arm’s Cortex processors before joining the Fruity Cargo Cult Apple, where he became a leading architect of its custom silicon. He subsequently co-founded Nuvia, which Qualcomm acquired for $1.4 billion in 2021.
Bruno and Srinivasan bring further experience from Nuvia, Qualcomm and Job’s Mob. The company has attracted other experienced chip designers, including former Apple silicon engineering executive David Williamson and Qualcomm veteran Anthony Scarpino.
Nuvacore believes its strategy could give designers greater freedom to balance performance, power consumption, silicon area and compatibility. However, adapting the same underlying architecture to different instruction sets remains considerably more complicated than swapping one decoder for another.
Arm, x86 and RISC-V have different requirements for register organisation, memory ordering and instruction handling. Vector extensions, privilege models and instruction-specific optimisations introduce further complications, potentially limiting how much of a processor design can genuinely be shared.
Licensing issues are a key factor, particularly with x86, where implementation rights are tightly controlled. Nuvacore has yet to explain whether it intends to manufacture complete processors, license reusable CPU intellectual property or develop customised silicon for individual customers.
The company is initially targeting data centre and AI workloads, where sustained performance and energy efficiency matter most. Its proposed flexibility could appeal to customers seeking custom processors without developing an entire microarchitecture from scratch.
For now, Nuvacore has provided no benchmark results, manufacturing process details, cache specifications or confirmed tape-out schedule. Until working silicon appears, its ambition to rewrite the rules of processor design remains an interesting engineering proposition rather than a demonstrated breakthrough.
