TSMC is squeezing the old EUV lemon instead of buying ASML’s priciest juicer.
At TSMC’s 2026 North American Technology Symposium, the firm laid out a roadmap running through 2029, with A13 and A12 pencilled in as the next die-shrunk steps.
One slide titled “TSMC Advanced Technology Roadmap” lines up the usual parade of nodes from N5P and N3E through to A14, then keeps going with A13 and A12 by 2029. The messaging is simple enough, more refinement, density and fewer excuses.
After N2 lands in first products this year, TSMC has N2P and N3A planned for 2026, then N2X and A16 in 2027. A14 and N2U sit in 2028, with A13 and A12 tagged for 2029.
TSMC previewed A13 as a 1.3nm shrink of A14, claiming six per cent area savings versus A14 and full backward compatibility. It is being pitched for HPC, AI and mobile work, with production targeted for 2029.
A12 is positioned as a further enhancement on the same A14 base, this time leaning on Super Power Rail for backside power delivery. TSMC says it is scheduled for production by 2029, keeping the marketing neat and the timelines conveniently far away.
On the N2 platform, TSMC is positioning N2U as a “balanced” option, promising speed gains of two to four per cent or power cuts of eight to 10 per cent at the same performance level. It claims a 1.02-1.03x logic-density bump over N2P and readiness for production in 2028.
Packaging got its own victory lap, with CoWoS moving to 5.5-reticle-sized products and bigger configurations queued behind it. TSMC says a 14-reticle CoWoS solution capable of integrating 10 compute dies and 20 HBM stacks is slated for production in 2028.
For 2029, TSMC is talking up SoW-X at a 40-reticle scale.
TSMC is pushing its SoIC stacking on the advanced platform too, with A14-to-A14 SoIC planned for production in 2029. It claims 1.8x higher die-to-die I/O density than N2-on-N2 SoIC, aiming for more bandwidth where it hurts.
Photonics is in the mix via TSMC-COUPE, with a true co-packaged optics setup using COUPE on substrate starting production in 2026. TSMC says it delivers 2x power efficiency and 10x latency reduction compared to a pluggable version on the board.
The spicy bit is what TSMC is not doing, leaning away from ASML’s High-NA EUV tools through 2029 and talking up “current EUV” life extension instead.
TSMC senior vice president Kevin Zhang said: “Whenever we see High-NA will provide meaningful, measurable benefit, we will do it. With A14, the enhancement I talked about earlier is very substantial without using High-NA. So, our technology team continues to find a way to extend the life of current EUV while harvesting the scaling benefit.”
