TSMC could raise CoWoS advanced packaging prices by up to 20 per cent as increasingly complex AI processors swallow available capacity.
According to China Times another round of increases is being discussed, with some packaging delivery times already lengthening. TSMC has not confirmed the proposed rise.
Customers desperate to secure production slots appear to have limited enthusiasm for haggling. The AI gold rush continues to be excellent business for whoever sells the shovels. Demand is spreading beyond AI GPUs into server CPUs and custom ASICs, while longer processor testing times are putting packaging and testing facilities under pressure together.
The problem extends beyond the number of chips being ordered. Designers are squeezing more compute dies and high-bandwidth memory stacks into individual packages, increasing their size and manufacturing complexity. Larger packages reduce equipment throughput, meaning manufacturers may need additional machinery even when the number of finished processors stays unchanged.
Throwing money at expansion offers no immediate escape. Industry sources estimate that a new advanced packaging facility takes roughly three years from groundbreaking to full utilisation at its bottleneck production stages.
Completed buildings and installed equipment still require calibration and validation before output becomes dependable. Constraints can shift between lithography, development and die-bonding operations as processes change. Equipment delivery times have reportedly stretched from three to six months to six to eight months, with upstream component and machining suppliers struggling to expand quickly.
Equipment makers say TSMC has bought machinery this year without its usual demands for discounts or extra functionality at the same price. Analysts cited in the report expect monthly CoWoS capacity to move beyond 130,000 wafers in 2026, with a target of 200,000 in 2027. Those figures are estimates, not confirmed company guidance.
TSMC chairman C.C. Wei reportedly told the company’s latest earnings briefing that five-reticle-size packages were in volume production with strong yields.
Nine- and 14-reticle-size versions remain in development, alongside panel-based CoPoS technology intended to support larger packages and reduce costs. The supplied comparison with Intel’s EMIB needs some qualification. CoWoS is a family of technologies, and not all larger-package variants rely on a full silicon interposer.
TSMC’s CoWoS-S uses a silicon interposer, while CoWoS-R uses redistribution layers. CoWoS-L combines redistribution layers with local silicon interconnects to provide dense connections where required.
Intel’s EMIB uses embedded silicon bridges and supports connections between logic dies and HBM. Chipzilla’s approach isn’t limited to modest interconnect requirements.
TSMC nevertheless benefits from customers’ existing designs, manufacturing relationships and qualification work. Moving an established accelerator to another packaging platform involves considerably more effort than changing the supplier’s name on a purchase order.
The reported expansion programme includes phased development at Chiayi AP7, equipment installation at Tainan AP8 P2 and additional SoIC capacity at AP6. A planned US advanced packaging facility, AP1, is expected to begin production in 2028.
