Samsung Electronics has delayed mass production of its Compute Express Link 3.1-based memory module, the CMM-D 3.0, which might have caused some headaches for Intel and AMD.
According to thelec the delay follows pushed-back launches of CXL 3.1-compatible server CPUs from Chipzilla and Advanced Micro Devices.
According to industry sources on 6 July, Samsung Electronics will keep making its CXL 2.0-based CMM-D 2.0 memory modules for now.
The company had planned to make customer samples of the CMM-D 3.0 in June, but that timetable has now been shoved into the long grass.
An industry source said: “The transition has been delayed as Samsung shifted additional production to CXL 2.0 products in line with current demand, while the CXL 3.1 ecosystem has yet to mature.”
“Any CXL 3.1 production in the fourth quarter this year is likely to be primarily for sample testing rather than commercial shipments.”
Full-scale mass production is now expected next year, which is not ideal for anyone selling tomorrow’s memory dream today.
CXL is an interconnect technology built on the Peripheral Component Interconnect Express (PCIe) interface. It uses different data transfer protocols but shares the same physical connector and bandwidth characteristics as PCIe.
CXL 3.1 is based on PCIe 6.0, while CXL 2.0 uses PCIe 5.0. Getting PCIe 6.0 performance needs a full set of compatible parts, including server CPUs, GPUs, SSDs and motherboards.
Most PCIe 6.0-ready components have yet to arrive, which makes commercial CXL 3.1 more roadmap than reality.
An industry source said: “Neither Intel nor AMD has released a CPU supporting PCIe 6.0.”
“The server industry will not be able to adopt CXL 3.1 until next-generation platforms such as Intel’s Diamond Rapids and AMD’s EPYC Venice become available.”
Intel had aimed to launch its Diamond Rapids server processor in the second half of this year.
That release has reportedly slipped to the second or third quarter of next year because of design changes and manufacturing yield issues.
AMD plans to launch its EPYC Venice processor in the second half of this year, with engineering samples already sent to major customers.
Samsung Electronics plans to produce CMM-D 3.1 samples validated on EPYC Venice-based systems after September.
Mass production will begin once customer qualification testing is completed. Industry sources expect commercial production to start in the first quarter of next year.
Samsung Electronics’ earlier roadmap called for sample products to be shown in late 2025.
At the Open Compute Project Global Summit in San Jose in October 2025, Samsung Electronics vice-president Song Taek-sang said the company would introduce the industry’s first CMM-D product supporting CXL 3.1 in the fourth quarter of 2025.
Attention has drifted away from CXL as demand piles into ordinary DRAM modules and high-bandwidth memory.
The slow development of the CXL 3.1 ecosystem is believed to have led Samsung Electronics to delay commercialisation.
SK hynix and Micron Technology have completed research and development of CXL 3.1-based memory modules. Neither company appears to be warming up the production lines, which tells you plenty about the state of the market.
CXL memory supports memory pooling, allowing memory resources to be shared through switching technology rather than tied to individual CPUs or GPUs.
That makes memory usage more efficient and can reduce the amount of memory required per processor.
The technology gives datacentres more flexibility by allowing modules to connect through external interfaces, rather like PC SSDs.
Samsung Electronics said: “While there have been adjustments to parts of our roadmap, we are continuing preparations to meet our planned mass production schedule without disruption.”
That appears to mean Samsung Electronics still thinks mass production could start inside the fourth quarter of this year, despite the ecosystem looking half-baked.
