Published in PC Hardware

Intel cuddles up to RISC-V

by on08 February 2022

Starts a $1 billion fund

Chipzilla has announced a new $1 billion fund on February 7 to build a foundry innovation ecosystem and will collaborate with several RISC-V standard IC design firms.

Meanwhile, RISC-V International, the global open hardware standards organization, announced that Intel has made deep investments and joined RISC-V International at the Premier membership level.

The fund is a collaboration between Intel Capital and Intel Foundry Services (IFS) to prioritise investments in capabilities that accelerate foundry customers' time to market - spanning intellectual property (IP), software tools, innovative chip architectures and advanced packaging technologies, according to Intel.

According to a Chipzilla press release it has made partnerships with several RISC-V IC design companies including Andes Technology, Esperanto Technologies, SiFive and Ventana Micro Systems.

Intel CEO [Kicking] Pat Gelsinger said: "Foundry customers are rapidly embracing a modular design approach to differentiate their products and accelerate time to market. Intel Foundry Services is well-positioned to lead this major industry inflection. With our new investment fund and open chiplet platform, we can help drive the ecosystem to develop disruptive technologies across the full spectrum of chip architectures,"

Intel's announcement to embrace RISC-V, is part of a cunning plan for it to become a new option for fabless semiconductor companies to consider, along with TSMC, Samsung, and Global Foundries.

Intel said it is joining forces with leading partners in the RISC-V ecosystem, including Intel Foundry Service, which plans to offer a range of validated RISC-V IP cores, performance-optimized for different market segments, in order to seize the opportunities brought by key strategic industry inflections: enabling modular products with an open chiplet platform and supporting design approaches that leverage multiple instruction set architectures (ISAs), spanning x86, Arm and RISC-V.


Last modified on 08 February 2022
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