Tom’s Hardware has got its paws on an ISSCC 2025 Advance Programme paper which says that Chipzilla’s 18A manufacturing process (1.8nm-class) will have an SRAM density closer to TSMC’s N3 (3nm-class) than its N2 (2nm-class). If this is correct than Intel’s process might not be as competitive.
The report said that Intel’s 18A process has a high-density SRAM bit cell size of 0.021 µm², resulting in an SRAM density of approximately 31.8 Mb/mm². This represents a notable improvement over Intel 4's 0.024 µm² bit cell size but aligns closely with TSMC’s N3E and N5 processes. By contrast, TSMC’s N2 technology achieves a significantly smaller SRAM bit cell size of 0.0175 µm², translating to a 38 Mb/mm² density.
While Intel’s SRAM density lags behind TSMC’s N2, it is essential to note that SRAM cell size is only one factor in evaluating a node’s overall competitiveness.
Intel’s 18A process introduces two transformative technologies: gate-all-around (GAA) transistors and a backside power delivery network (BSPDN). BSPDN enhances power delivery efficiency, potentially boosting transistor performance and allowing for increased logic density. This innovation may provide Intel with an edge in logic-heavy designs, even if its SRAM density trails TSMC’s.
The ISSCC noted: "Although modern chip designs use plenty of SRAM and its density is crucial for node-to-node scaling, logic density is more important than HDC SRAM density."
Unfortunately, direct comparisons of logic density between Intel’s 18A and TSMC’s N2 remain unavailable due to variations in library configurations and usage patterns.
Scaling SRAM density has become increasingly challenging due to modern memory cells' stringent design and operational requirements. Variability at smaller nodes often limits the potential for aggressive scaling without compromising stability or reliability. As a result, some advanced nodes may feature larger SRAM cells compared to their predecessors.
Despite these hurdles, TSMC has aggressively reduced SRAM cell size with its N2 process, a marked improvement over its earlier FinFET-based nodes. In comparison, Intel’s modest SRAM density gains come alongside significant advances in transistor technology and power delivery, reflecting a balanced approach to node development.
Both TSMC’s N2 and Intel’s 18A processes rely on GAA transistors, a significant shift from FinFET-based architectures. While TSMC has focused on maximising SRAM density, Intel prioritises power efficiency and logic density through BSPDN.
Intel’s decision to align its SRAM density with TSMC’s N3E and N5 processes could indicate a strategic focus on holistic improvements rather than SRAM scaling alone. As more details emerge about power consumption and logic density, the industry will gain a clearer picture of how Intel’s 18A compares to TSMC’s N2 in real-world applications.
