This processor is on track to be available next year. More importantly, it will be manufactured using TSMC's advanced 2nm (N2) process technology.

To our knowledge, Venice features a Zen 6-based architecture composed entirely of high-performance big cores. This announcement appears potentially reactionary to Intel's Clearwater Forest Intel18A all E-core announcement. This Data center high-density part is expected in early 2026.

Some colleagues have already pointed out that while Intel's 18A process might offer higher performance, TSMC's N2 process is expected to provide greater density. In a related development, AMD also announced the successful bring-up and validation of its current 5th Gen AMD EPYC CPU products at TSMC’s new fabrication facility in Arizona.

This move underscores AMD's commitment to U.S. manufacturing. It's worth noting that the current EPYC 5th Gen products are 3nm-based. Based on current information, the N2 process required for Venice will be available next year, initially at TSMC's Baoshan plant (Fab 20) in Hsinchu, Taiwan. Industry sources suggest Apple is the so-called "pipe cleaner" and lead customer for TSMC's N2 node overall, while AMD appears positioned to be a leading consumer for high-performance silicon (HPC) parts manufactured using the N2 process.