According to a briefing from Avinash Sodani, Knights Landing Chief Architect at Intel, a product update by Hugo Saleh, Marketing Director of Intel's Technical Computing Group, an interactive technical Q&A and a lab demo of a Knights Landing system running on an Intel reference-design system, Nvidia could be Intel's target.

Knights Landing and prior Phi products are leagues apart and more flexible for a wider range of uses. Unlike more specialized processors, Intel describes Knights Landing as taking a "holistic approach" to new breakthrough applications.

The current generation Phi design, which operates as a coprocessor, Knights Landing incorporates x86 cores and can directly boot and run standard operating systems and application code without recompilation.

The test system had socketed CPU and memory modules was running a stock Linux distribution. A modified version of the Atom Silvermont x86 cores formed a Knights Landing 'tile' which was the chip's basic design unit consisting of dual x86 and vector execution units alongside cache memory and intra-tile mesh communication circuitry.

Each multi-chip package includes a processor with 30 or more tiles and eight high-speed memory chips.

Intel said the on-package memory, totalling 16GB, is made by Micron with custom I/O circuitry and might be a variant of Micron's announced, but not yet shipping Hybrid Memory Cube.

The high-speed memory is similar to the DDR5 devices used on GPUs like Nvidia's Tesla.

It looks like Intel saw that Nvidia was making great leaps into the high performance arena with its GPU and thought "I'll be having some of that."

The internals of a GPU and Xeon Phi are different, but share common ideas.

Nvidia has a big head start. It has already announced the price and availability of a Titan X development box designed for researchers exploring GPU applications to deep learning. Intel has not done that yet for Knights Landing systems.

But Phi is also a hybrid that includes dozens of full-fledged 64-bit x86 cores. This could make it better at some parallelizable application categories that use vector calculations.