Intel thinks that by integrating the FPGA and the HBM2, Intel Stratix 10 MX FPGA can increase bandwidth for applications that require hardware accelerators to speed up mass data movements and stream data pipeline frameworks.

The gear is great for HPC environments where the ability to compress and decompress data before or after mass data movements is really important. HBM2-based FPGAs can compress and accelerate larger data movements much faster than stand-alone FPGAs.

With High Performance Data Analytics (HPDA) environments, streaming data pipeline frameworks like Apache* Kafka and Apache* Spark Streaming require real-time hardware acceleration. Intel Stratix 10 MX FPGAs can simultaneously read/write data and encrypt/decrypt data in real-time without burdening the host CPU resources.

The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 gigabytes per second with the integrated HBM2. HBM2 vertically stacks DRAM layers using silicon via (TSV) technology.

These DRAM layers sit on a base layer that connects to the FPGA using high density micro bumps. The Intel Stratix 10 MX FPGA family uses Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) that speeds communication between FPGA fabric and the DRAM. EMIB works to efficiently integrate HBM2 with a high-performance monolithic FPGA fabric, solving the memory bandwidth bottleneck.

Intel is shipping several Intel Stratix 10 FPGA family variants, including the Intel Stratix 10 GX FPGAs (with 28G transceivers) and the Intel Stratix 10 SX FPGAs (with embedded quad-core ARM processor).

The Intel Stratix 10 FPGA family utilizes Intel’s 14 nm FinFET manufacturing process and incorporates what Chipzilla calls state-of-the-art packaging technology, including EMIB.