Intel's Research Components Group introduced the work in papers at an international conference being held in San Francisco. The Silicon Valley company is working to regain a lead in making the smallest, fastest chips that it has lost in recent years to rivals like TSMC and Samsung.

Intel CEO Pat Gelsinger laid out commercial plans aimed at regaining that lead by 2025, but this shows how Intel will compete beyond 2025.

One of the ways Intel is packing more computing power into chips by stacking up "tiles" or "chiplets" in three dimensions rather than making chips all as one two-dimension piece.

Intel showed work that could allow for 10 times as many connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.

One research paper demonstrated a way to stack transistors on top of one another.

Intel believes the technology will yield a 30- 50 per cent increase in the number of transistors it can pack into a given area on a chip.

Paul Fischer, director and senior principal engineer of Intel's Components Research Group said that stacking the devices directly on top of each other, meant Intel could save area.

"We're reducing interconnect lengths and really saving energy, making this not only more cost efficient, but also better performing."