In his own words, he describes it as "seven advanced silicon technologies in a single package Silicon engineers dream a thing of beauty".
Ponte Vecchio has to be one of the most complex chips ever, as matching seven different silicon technologies and making it work via some interconnect is anything but easy.
Xe HPC uses new Foveros Co EMIB packaging combining base tile, compute tile, Rambo cache tile, and Xe link I/O in a single chip. Intel confirmed that it is using Intel 10nm SUperfin, second-generation 10nm, Intel's next-generation process, as well as the advanced external process. It also combines pieces of Intel 10 nm enhanced Superfin and external.
There are few more details than that, but it will be a good competitor in the HPC market if all goes well.