We couldn't resist comparing Nehalem design with Barcelona / Deneb design and Nehalem’s chief architect strongly disagreed with our comments.

He said that Nehalem can do 4 wide instructions, while Barcelona / Deneb can do only three. Nehalem has much lower latency cache and at the same time, it has 8MB L3 cache that is much more than Barcelona.

Its memory controller is DDR3, while AMD is still stuck with DDR2, at least with Barcelona K10 design; and last, but not the least, even when AMD goes for DDR3, Intel will have a three-channel memory advantage.

Nehalem shares a lot of engineering similarities to Barcelona K10 and Deneb K10.5 in 45nm as it's a native quad-core, has shared L3 cache memory, an integrated memory controller, but at the same time it has Turbo and Hyper Threading; something that AMD doesn’t have and doesn’t plan to have anytime soon.

Ronan also concluded that “smart people often come to the same ideas,” but for us it's more likely that Intel embraced some of the good ideas that AMD had for years and implemented them into its Nehalem design.