Finding intermittent errors in a chip is a nightmare particularly as SoC design it is becoming more complex.
UltraSoC told Electronics Weekly says that the problem arises when designs use shared resources on the chip such as bus bandwidth and memory.
Bus deadlocks come about when a processor can be waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives.
Gadge Panesar, UltraSoC, chief technology officer thinks he has fixed the problem by adding deadlock detection to its SoC analysis, profiling and debug.
"Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs. These conditions are a major contributor to the current crisis in the SoC industry," he said.
UltraSoC's approach is to allow designers to "look inside" the SoC design at wire speed, during normal operation.
This is all bleeding edge stuff and it is unclear how much of these designs will be adopted. UltraSoC is mostly focused on Arm designs and it will demonstrate its new deadlock detection capabilities at ARM TechCon in November.