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Europeans run first successful RISC V processor accelerator

by on23 September 2021


Moving to home grown super computers

The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC).

The move is seen as an initial step towards homegrown supercomputing hardware. EPI, launched back in 2018, aims to increase the independence of Europe's supercomputing industry from foreign technology companies. At its heart is the adoption of the free and open-source RISC-V instruction set architecture for the development and production of high-performance chips within Europe's borders.

The project's latest milestone is the delivery of 143 samples of EPAC chips, accelerators designed for high-performance computing applications and built around the free and open-source RISC-V instruction set architecture.

Designed to prove the processor's design, the 22nm test chips ironically fabbed at GlobalFoundries have passed initial testing, running a bare-metal "hello, world" program as proof of life.

It's a rapid turnaround. The EPAC design was proven on FPGA in March and the project announced silicon tape-out for the test chips in June -- hitting a 26.97mm2 area with 14 million placeable instances, equivalent to 93 million gates, including 991 memory instances.

While the FPGA variant, which implemented a subset of the functions of the full EPAC design, was shown booting a Linux operating system, the physical test chips have so far only been tested with basic bare-metal workloads -- leaving plenty of work to be done.

Last modified on 23 September 2021
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